1. Run example 33.2: Trench Isolation Example in Athena_Complex. Notice mesh distribution to incorporate curvatures of the structure. Modify your etching process to round the trench corners (why do we need it?). Compare oxide thickness grown on poly-Si and c-Si in the same oxidation process (what causes the differences?). Could we use oxide filling only instead of poly-Si?
2.Run example 33.6: Trench Formation and Planarization in Athena_Complex. It combines severals steps (including LOCOS) that eventually result in a palnar structure. What are the main fabrication difficulties in this design? Compare overall performance (improvement or degradation) with that of trench isolation from example 33.2.
3.Run example 31.32: Metal Void Formation and example 31.13: Interconnect Metallization in Athena ELITE. How can avoid void formation? Discuss the the effect of deposition process and thicknesses of dielectric and of metal layers on degradation of interconnects.
5. Run the example #33.5 (Multilevel interconnect formation). After each processing step pause and display the structure files in TonyPlot. Identify each step and explain its meaning in silicon processing, the role of materials used (e.g.. BPSG vs. TEOS, TiN vs. W or Al, etc.) and the process parameters/models involved (partially isotropic vs. anisotropic etch, smooth in deposition etc.).
6. Ruch examples 31.25, 31.26, and 31.27 illustrating CPM processes. Identify parameters that can be controlled in the polishing processes to obtain correct planarization of fabricated structures. Notice differences in polishing rates and resulting dishing effect. Propose solutions.
Each project has to be written individually (one person - one unique report) even though you are encouraged to work in groups on the simulations.
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