Please read the questions carefully to include the main aspects of the problems. Answer concisely but thoroughly.
1. In silicide formation, depending on the type of metal used, either Si or the metal is a dominant diffuser. For CoSi2 - Co is the diffuser, while for TiSi2 it is Si. How can you use this information to design you contact scheme to shallow junctions? Is this information enough for optimization of contacts to junctions in VLSI/ULSI circuits? What else has to be included in designing the correct process flow? Please use the CMOS technology to justify your answer. Hint: look at junctions but consider other steps that follow direct contact formation.
2. Sketch processing sequence used for the BJT fabrication shown in Fig. 7.41b. a) Discuss the role of intrinsic and extrinsic base regions from the perspective of device operation and fabrication. b) How would you design/make the emitter region to have the best BJT operation (define what you consider the best performance). Refer to your Sem_Dev simulation while answering this question.
3. How does the scaling down of MOS transistors affect the subthreshold swing? How will the SS parameter deterioration (is it an increase or decrease of SS?) compare for NMOS and PMOS transistors? Assume the same device dimensions. Justify your answer and refer to your SILVACO simulation observation.
4. What , in your opinion is (are) the bottle neck(s) of future ULSI chip fabrication? Use BiCMOS as your technology. Hint: you have to make assumptions as to the circuit objectives (speed, power, etc.).
Example II
Please limit your answer to max. 2 pages.
1.What are the main issues in optimization of a LOCOS process?
2. Discuss limitations of silicide technologies for contact formation in scale down devices. What are the solutions for contact formation in such small devices?
3. How do we control threshold voltage in n- and p-channel MOS transistors. Why buried channel devices are more susceptible to short channel effects?
4. Describe briefly the latch-up effect? What are the means to reduce it?
5. Why polysilicon emitter transistors are better than a single crystalline BJTs? How and why do we incorporate the polysilicon based process in the base fabrication?
6. Why do we need LDD structures in MOS technology? Does it solve all the problems in scaled down devices?
7. What and why do we compromise in low cost BICMOS circuits?
8. Which of the SOI techniques looks the most promising? Look for a winner.