Chip Gallery

• Ditigal PLL-based CDR (Inductor Coupling DCO)

• 150MHz Bandwidth CT ΔΣ ADC

• Rad-Tolerant DLL for DDR2 Interface

• Frequency Synthesizer for Multistandard Wireless Receiver

• 0.4-6 GHz Frequency Synthesizer for SDR

• Low Jitter 16GHz ADPLL with Inductor-Coupled DCO

• 16-Gb/s 0.98-pJ/bit/s Wireline Receiver

• 12GHz 67% Tuning Range Low RMS Jitter PLL

• Radiation-Tolerant Ring Oscillator PLL

• Wideband Millimeterwave Frequency Synthesizer

• 25 GS/s 6-bit Flash ADC

• 10-bit 500MS/s 6.7fJ/conv.-s SAR ADC with a Doube-Rate Comparator

• 10-bit 2.4GS/s 17.7fJ/conv.-s Time-Interleaved SAR ADC

• 8-bit 1GS/s 12.01fJ/conv.-s Pipeline SAR ADC

• 66-81 GHz LNA

• W-band PA

• mmW PLL for 5G Wireless Communication

• SiPM ROIC